1. Field of the Invention
The present invention relates to an exception processing method for processing an interruption at a high speed and an information processing apparatus in which an exception processing control unit used for performing the exceptional processing method is downsized.
2. Description of the Related Art
An arithmetic function is generally classified into five stages of an instruction reading operation (IF), an instruction decoding operation (ID), an arithmetic operation (EX), a memory accessing operation (MA) and a write-back operation (WB). A microprocessor (or an information processing apparatus,) in which pipe line processing is performed by executing the five stages in parallel, is well known. A stream of a general five-stage pipeline is shown in FIG. 1.
2.1. Previously Proposed Art
FIG. 2 is a block diagram of a conventional micro processor. As shown in FIG. 2, a conventional micro processor 11 is composed of a decoder section 12 for reading an instruction transmitted through a data bus 13 and decoding the instruction, a data pass section 14 for performing an arithmetic operation, a logical operation and a shift operation for data transmitted through a register file under an control of the instruction transmitted from the decoder section 12 through a control bus L1, an exception processing generating source 16 for generating an interruption occurring signal at a time of an interruption occurrence and transmitting the interruption occurring signal to the decoder section 12 through an interruption occurring signal line L2, a random access memory (RAM) 18 connected to the data bus 13 and an address bus 19 for temporarily storing data processed in the data pass section 14, and a read only memory (ROM) 20 connected to the data bus 13 and the address bus 19 for storing pieces of data and instructions transmitted to the decoder section 12 and the data pass section 14. A central processing unit (CPU) is composed of the decoder section 12 and the data pass section 14.
The decoder section 12 is composed of a normal processing sequential control unit 21 for controlling a normal processing routine performed according to a normal processing program stored in the ROM 20, an exception processing sequential control unit 22 for controlling an exception processing routine performed according to an exception processing program stored in the ROM 20 in cases where the interruption occurring signal generated in the exception processing generating source 16 is received, and a decoding unit 23 for decoding an instruction transmitted from the ROM 20 according to the normal processing or the exception processing performed by the normal processing sequential control unit 21 or the exception processing sequential control unit 22 when a control signal is transmitted from the normal processing sequential control unit 21 or the exception processing sequential control unit 22 through a control line L3.
The data pass section 14 is composed of an arithmetic logic unit (ALU) 24 for performing a logical operation, an arithmetic operation, a shift operation and the like for the data, a register file 25 for storing an arithmetic result obtained in the ALU 24, a program counter 26 for counting an address of a program currently used, and an address unit 27 for selecting an output of an operation result obtained in the ALU 24 to the address bus 19 or an output from the program counter 26 to the address bus 19.
The program counter 26 has a 32-bit program counter (PC) register 28 and a 32-bit processor state register (PSR) 29.
In the IF stage, the program counter 26 is operated. In the ID stage, the decoder section 12 and the register file 25 are operated. In the EX stage, the ALU 24 is operated. In the MA stage, the address unit 27 is operated, In the WB stage, the register file 25 is operated.
In the above configuration of the conventional micro processor 11, when an operational state of the microprocessor 11 is changed from a normal processing state to an exception processing state because of the occurrence of an interruption, saving of a condition of an interrupted program (a first operation) and a branching operation to an exception processing routine placed at a branch address (a second operation) are performed in the conventional microprocessor 11.
The condition of the interrupted program in the first operation denotes an interrupted instruction of the program stored in a condition register and an address of the interrupted instruction, and the program condition is saved in the RAM 18 or an internal register (not shown) of the microprocessor 11.
The setting of the branch address is performed according to one of two methods in the second operation. One method is a vector interrupting method in which an address relating to the branch address is transmitted from the exception processing generating source 16 to the exception processing sequential control unit 22. The other method is a non-vector interrupting method in which branching information including the branch address is stored in the ROM 20 in advance and the branch address is transmitted from the ROM 20 to the exception processing sequential control unit 22.
The vector interrupting method is classified into a memory direct addressing technique and a memory indirect addressing technique (refer to "Computer Architecture" written by Takanobu BABA and published on Jun. 24, 1996). In the memory direct addressing technique, the branch address is transmitted from the exception processing generating source 16 to the exception processing sequential control unit 22. In the memory indirect addressing technique, the branch address is stored at a reference address of a memory unit represented by the ROM 20, the reference address or a difference (called an offset value) between a base address and the reference address is transmitted from the exception processing generating source 16 to the exception processing sequential control unit 22, and a value of the branch address stored at the reference address of the ROM 20 is transmitted to the exception processing sequential control unit 22.
In a first conventional exception processing method performed according to the memory indirect addressing technique, a state transition of the microprocessor 11 from a normal processing state to an exception processing state is shown in FIG. 3.
When the microprocessor 11 is set in a normal program executing condition to execute a particular normal program (step S210), it is judged whether or not an interruption to the particular normal program occurs (step S220). In cases where an interruption occurs, the occurrence of the interruption is transmitted from the exception processing generating source 16 to the exception processing sequential control unit 22, a program state of the interrupted program registered in a stack of the PSR 29 initially is saved in the RAM 18 (step S230), contents of a stack of the PC register 28 take refuge in the RAM 18 (step S240), an offset value used to specify an exception processing vector is loaded from the exception processing generating source 16 to the exception processing sequential control unit 22 (step S250), an address of the exception processing vector is calculated in the ALU 24 by using the offset value and a base address (step S260), the exception processing vector stored in the ROM 20 is specified according to the address of the exception processing vector transmitted through the address bus 19, the exception processing vector is loaded from the ROM 20 to the data pass section 14 through the data bus 13 (step S270), the exception processing vector is set in the PC register 28 (step S280), and an operational state of the microprocessor 11 is branched to an exception processing routine (step S290). In this case, a data value stored at an address of the ROM 20 which is indicated by a value of the exception processing vector is the branch address, and the branch address denotes an exception processing starting address.
FIG. 4 shows a stream of pipeline processing indicating the above procedure.
As shown in FIG. 4, when an interruption signal Sin is input from the exception processing generating source 16 to the exception processing sequential control unit 22 in an ID stage 401 in which an instruction 400 is executed, the operation of the normal processing sequential control unit 21 is stopped, and the operation of the exception processing sequential control unit 22 is started. That is, a first instruction 400' is output from the exception processing sequential control unit 22 in the ID stage 401 of the instruction 400, a storage address of the RAM 18 for the PSR 29 is calculated in an EX stage of the instruction 400, a program state of the interrupted program registered in a stack of the PSR 29 initially is saved in the RAM 18 in an MA stage 402 of the instruction 400. Also, a second instruction 410 is output from the exception processing sequential control unit 22, a storage address of the RAM 18 for the PC 28 is calculated in an EX stage of the second instruction 410 in synchronization with the MA stage 402, and contents of a stack of the PC register 28 is saved in the RAM 18 in a MA stage 403 of the second instruction 410. Also, a third instruction 420 is output from the exception processing sequential control unit 22, a value of a reference address at which an exception processing vector indicating a branch address is stored in the ROM 20 or an offset value from a base address is calculated in an EX stage of the third instruction 420 in synchronization with the MA stage 403, and the value of the reference address or the offset value is loaded from the exception processing generating source 16 to the exception processing sequential control unit 22 in an MA stage 404 of the third instruction 420. Also, a fourth instruction 430 is output from the exception processing sequential control unit 22, IF and ID stages are performed, and any EX, MA or WB stage is not performed. Also, a fifth instruction 440 is output from the exception processing sequential control unit 22, the value of the reference address is set in the PC register 28 in an EX stage 405 of the fifth instruction 440 in cases where the value of the reference address is loaded in the MA stage 404, a value of a reference address calculated from the offset value and a base address is set in the PC register 28 in the EX stage 405 in cases where the offset value is loaded in the MA stage 404, and the exception processing vector placed at the reference address is loaded from the ROM 20 to the data pass section 14 in an MA stage 406 of the fifth instruction 440. Also, a sixth instruction 450 is output from the exception processing sequential control unit 22, IF and ID stages are performed, and any EX, MA or WB stage is not performed. Also, a seven instruction 460 is output from the exception processing sequential control unit 22, the loaded data (the exception processing vector) is set in the PC register 28 in an EX stage 407 of the seven instruction 460. Also, an eighth instruction 470 is output from the exception processing sequential control unit 22, IF and ID stages are performed, and any EX, MA or WB stage is not performed. That is, the MA stage 402, the MA stage 403, the MA stage 404, the EX stage 405, the MA stage 406 and the EX stage 407 are performed in that order. Thereafter, a ninth instruction 480 is output from the exception processing sequential control unit 22 in synchronization with the EX stage 407, IF and ID stages are performed, and any EX, MA or WB stage is not performed. Thereafter, a tenth instruction 490 is output from the exception processing sequential control unit 22, and an exception processing routine is started. In this case, an interruption response is 10 cycles. Therefore, it is required to decode 9 cycles of the instructions 400' to 480 in the decoding unit 23 under the control of the exception processing sequential control unit 22 for the purpose of performing the control in the EX stage 407.
Also, in a second conventional exception processing method performed according to the memory direct addressing technique, the change of an operational state of the micro processor 11 from a normal processing state to an exception processing state is shown in FIG. 5.
When the microprocessor 11 is set in a normal program executing condition to execute a particular normal program (step S210), it is judged whether or not an interruption to the particular normal program occurs (step S220). In cases where an interruption occurs, the occurrence of the interruption is transmitted from the exception processing generating source 16 to the exception processing sequential control unit 22, a program state of the interrupted program registered in a stack of the PSR 29 initially is saved in the RAM 18 (step S230), contents of a stack of the PC register 28 is saved in the RAM 18 (step S240), an exception processing vector is loaded from the exception processing generating source 16 to the exception processing sequential control unit 22 (step S310), the exception processing vector is set in the PC register 28 (step S320), and an operational state of the microprocessor 11 is branched to an exception processing routine (step S330).
FIG. 6 shows a stream of pipe line processing indicating the above interruption response of the microprocessor 11 to an exceptional processing state.
As shown in FIG. 6, when an interruption signal Sin is input from the exception processing generating source 16 to the exception processing sequential control unit 22 in an ID stage 301 in which an instruction 300 is executed, the operation of the normal processing sequential control unit 21 is stopped, the operation of the exception processing sequential control unit 22 is started, and a plurality of instruction processing cycles in which an EX stage is again executed after three MA stages are executed is performed. That is, a first instruction 300' is output from the exception processing sequential control unit 22 in the ID stage 301 of the instruction 300, a storage address of the RAM 18 for the PSR 29 is calculated in an EX stage of the instruction 300, a program state of the interrupted program registered in a stack of the PSR 29 initially is saved in the RAM 18 in an MA stage 302 of the instruction 300. Also, a second instruction 310 is output from the exception processing sequential control unit 22, a storage address of the RAM 18 for the PC 28 is calculated in an EX stage of the second instruction 310 in synchronization with the MA stage 302, and contents of a stack of the PC register 28 is saved in the RAM 18 in an MA stage 303 of the second instruction 310. Also, a third instruction 320 is output from the exception processing sequential control unit 22, a branch address is calculated in an EX stage of the third instruction 320 in synchronization with the MA stage 303, and the branch address is loaded from the exception processing generating source 16 to the exception processing sequential control unit 22 in an MA stage 304 of the third instruction 320. Also, a fourth instruction 330 is output from the exception processing sequential control unit 22, IF and ID stages are performed, and any EX, MA or WB stage is not performed. Also, a fifth instruction 340 is output from the exception processing sequential control unit 22, and the branch address is set in the PC register 28 in an EX stage 305 of the fifth instruction 340. Also, a sixth instruction 350 is output from the exception processing sequential control unit 22, IF and ID stages are performed, and any EX, MA or WB stage is not performed. Also, a seventh instruction 360 is output from the exception processing sequential control unit 22, IF and ID stages are performed, and any EX, MA or WB stage is not performed.
Thereafter, an instruction 370 is output from the exception processing sequential control unit 22, and an exception processing routine is started. In this case, an interruption response is 7 cycles of the instructions 300', 310, - - - , 350 and 360.